An I2C timing diagram shows two wires, SCL and SDA, and the moments that matter: start, each bit while the clock is high, acknowledge, and stop. A complete write of 0x0F to the 7-bit address 0x50 is drawn on the examples page. This page names the events and the intervals from the I2C specification.
Understanding I2C Timing Diagrams
I2C (Inter-Integrated Circuit) is a two-wire serial protocol used extensively in embedded systems for connecting sensors, EEPROMs, displays, and other peripherals. I2C timing diagrams are essential for understanding and documenting how the protocol works.
I2C Signal Overview
- SCL (Serial Clock) – Clock signal generated by the master
- SDA (Serial Data) – Bidirectional data line
Both lines are open-drain with pull-up resistors, meaning devices can only drive the line low. This allows for multi-master operation and clock stretching.
Key I2C Timing Events
- START condition – SDA falls while SCL is high
- STOP condition – SDA rises while SCL is high
- Repeated START – START without preceding STOP
- ACK/NACK – Acknowledge bit after each byte
- Clock stretching – Slave holds SCL low to slow communication
How to read a write frame
Both wires idle high. Start is SDA falling while SCL stays high. Each following bit is the SDA level during the high half of SCL. The first seven bits are the address. The eighth bit is direction: 0 for write, 1 for read. The ninth bit is the acknowledge, driven by the peripheral. Data bytes repeat that pattern of eight bits plus an acknowledge. Stop is SDA rising while SCL is high. Clock stretching is the peripheral holding SCL low. The worked frame does not stretch the clock.
Draw the two rows in the editor. The handbook covers labels and export.
Documenting I2C Timing Parameters
The I2C specification sets minimum times. Standard mode is up to 100 kHz. Fast mode is up to 400 kHz. The numbers below are the usual minimums from that specification, so a diagram can label the interval even when the drawing itself uses equal slots:
| Parameter | Description | Standard Mode | Fast Mode |
|---|---|---|---|
| fSCL | Clock frequency | 100 kHz | 400 kHz |
| tHD;STA | Hold time START | 4.0 µs | 0.6 µs |
| tSU;STA | Setup time repeated START | 4.7 µs | 0.6 µs |
| tSU;STO | Setup time STOP | 4.0 µs | 0.6 µs |
| tSU;DAT | Data setup time | 250 ns | 100 ns |
| tHD;DAT | Data hold time | 0 ns | 0 ns |
The same frame shape covers a sensor read, an EEPROM page write, or a display command. What changes is the address and the data bytes, not the start, acknowledge, and stop rules.
Related: worked SPI, I2C, and UART frames · SPI timing · open the editor